Generally, integrated circuit technology is based on the ability to form numerous transistor structures in a single silicon substrate (on a silicon die). Generally, there are two basic types of transistor structures: (1) bipolar and (2) field effect. In bipolar transistors, a `base` structure is disposed between and in contact with an `emitter` structure and a `collector` structure. In field effect transistors (FETs) there are two spaced-apart `source` and `drain` structures (or regions, analogous to the `emitter` and `collector` of a bipolar transistor). In an FET, a channel is induced in the surface of the silicon region between the source and drain regions, and tunnelling of charges between the source and drain is controlled by a `gate` element (analogous to the `base` of a bipolar transistor) disposed atop the channel. In some instances, the gate element of an FET is insulated from the channel, forming a so-called Insulated Gate FET (IGFET).
Generally, the emitter/base/collector or source/drain regions of a transistor structure are formed by implanting ions (dopants), such as phosphorous or boron, into a surface of a semiconductor substrate. An n-type or a p-type region may be formed, depending on the polarity of the dopant. Usually, in order form two dissimilarly doped regions adjacent one another (i.e., for a single transistor structure), it is required to mask the substrate with
It is commonly required that several transistor structures are formed on a single semiconductor die, and that the individual transistor structures are packed as closely together (to one another) as possible. This generally requires some sort of isolation structure to be formed between adjacent transistor structures. To this end it is known, for example, to mask portions of the substrate that are intended to be implanted to form elements of transistor structures, and to thermally grow a silicon dioxide structure in un-masked areas of the substrate. One such technique is known as Local Oxidation of Silicon (LOCOS). Such LOCOS structures tend to grow not only above the surface of the substrate, but tend to grow into the substrate as well. The portion of the LOCOS structure that grows above the surface of the substrate is exemplary of a situation that affects nearly every semiconductor device--namely non-planar topology of the top surface of the substrate.
Additional layers and structures formed atop the basic transistor structures, to implement devices such as non-volatile memory (for example), or simply to effect interconnections between many of these structures on a substrate (e.g., on an integrated circuit die), evidently cause the top surface of the substrate to become very irregular (non-planar; topological). Interconnections, for example, typically require several alternating layers of insulating material and conductive material, and vias or plugs through the layers to make contact to other metal layers and to the underlying elements of the transistor structures. When applying subsequent layers, these topological features can present difficulties in obtaining layers of uniform thickness, good coverage at steps, uniform filling of vias, and the like. Hence, it is known to planarize the layers of a semiconductor device at various stages of fabrication.
An irregular topological feature certainly occurs when, for example, a FET gate electrode is formed atop a thin (e.g. 2 nm) layer of insulating material such as oxide and a thicker (e.g., 50 nm) layer insulating material such as nitride (silicon nitride). The gate electrode forms a rather prominent feature which tends to be elevated from the remaining surface of the transistor structure.
Numerous iterations of one or more of the aforementioned transistor structures, or the like, can be replicated and interconnected on an integrated circuit to effect complex circuit functions. In some instances, two neighboring (adjacent) transistors that are intended to be interconnected can share an element (such as a source or drain) with one another, thereby avoiding interconnection through overlying metal layers.
In a typical complementary-metal-oxide-semiconductor (CMOS) transistor structure, two complementary (opposite polarity) transistors are formed adjacent one another. For example, a first area of a substrate is masked (e.g., with photoresist) and another, second adjacent area is doped to form an N-Well in the second area. The first area is prevented from being doped by the mask material overlying the first area. Then the mask is stripped and a second mask is applied over the N-Well. The now-exposed first area is doped to form a P-Well. In this step, the mask overlying the N-Well prevents the N-Well from being doped during the P-doping step. Source and Drain implants for the N-Well and P-Well proceed in much the same manner, typically requiring one of the N- or P-Wells to be masked while the other is being implanted. The Source and Drain regions are typically doped to a polarity opposite to that of the well in which they reside.
Desirable objects of semiconductor design, generally, include minimizing process steps, ensuring reliable fabrication of various structures, and achieving desired functionality. Often, these goals may compete against one another. Hence it is desirable, for a given intended semiconductor design, to implement steps (or a series of steps in an overall fabrication scheme) that can achieve one or more of these objectives, without detracting from another of the objectives. For example, if one layer can serve two functions (e.g., as an insulating layer and as an implant mask), this would generally be considered desirable.
Another factor of concern in semiconductor design is thermal budget. As mentioned above, isolation structures are often formed using a thermal process. Such application of heat to a substrate will also have the effect of diffusing (spreading) out fugitive ionic species (dopants) that have already been implanted into the substrate. While, in some cases, such diffusion of implants is advertent, in other cases it is an unwelcome side effect of other fabrication processes. In either case, any thermal processing of the substrate subsequent to implantation must be accounted for in the design of the process and of the device. As an example, it is known to deposit, densify and re-flow a layer of glass to establish a planar top surface of an in-process substrate, for example so that subsequent layers can reliably be applied. Each of these steps requires a thermal cycle at an elevated temperature. In the case of depositing, densifying and re-flowing a glass layer, which would typically occur after several implants have already been performed, the re-flow step (in particular) places an enormous strain on the thermal budget of the process.